View PT7C43390CZEE_8920052.PDF datasheet online --- IC-ON-LINE

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|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| real - time clock module 2 015 - 12 - 000 1 pt0 280 - 8 12 / 11 /1 5 1 pt7c43390 /43390c features ? low current consumption: 0. 3 a typ. (v dd =3 .0v, t a = 25c) ? wide operating voltage range: 1.3 5 to 5.5 v ? minimum tim e keeping operation voltage: 1. 25 v ? built - in clock adjustment function ? built - in free user register ? 2 - wire ( i 2 c - bus ) cpu interface ? buil t - in alarm interrupter ? built - in flag generator at power down or power on ? auto calendar up to the year 2099, automatic leap year calculation function ? built - in constant voltage circuit ? built - in 32 khz crystal oscillator circuit ? built - in 32 khz crystal for p t7c43390c ? package : soi c - 8l, ts sop - 8l, and t d fn 2 x3 - 8l for pt7c43390 ; t dfn4x4 - 8l for pt7c43390c applications ? mobile game device , mobile phone ? industrial control ? electronic power meter ? dvd recorder ? car navigation ? ip camera, dvr, nvr description the pt7c43 3 90 is a cmos i 2 c - bus real - time clock ic , which operates with the very low current consumption and in the wide range of operation voltage. the operation voltage is 1.3 5 v to 5.5 v so that the rtc can be used for various power supplies from main supply to backu p battery. in the system which operates with a backup battery, the included free registers can be used as the function for users backup memory. users always can take back the information in the registers which is stored before power - off the main power sup ply, after the voltage is restored. the ic has the function to correct advance / delay of the clock data speed, in the wide range, which is caused by the oscillation circuits frequency deviation. correcting according to the temperature change by combining this function and a temperature sensor, it is possible to make a high precise clock function which is not affected by the ambient temperature. function table item function pt7c43390 pt7c43390 c 1 oscillator source crystal * external crystal integral cr ystal 2 time time display 12 - hour ? ? 24 - hour ? ? 3 interrupt alarm interrupt pin output ? 2 ? 2 timer interrupt output ? ? 4 programmable square wave output (hz) 1hz,2hz,4hz 8hz,16hz 32khz 1hz,2hz,4hz 8hz,16hz 32khz 5 communication 2 - wire i 2 c bus ? ? burst mode ? ? 6 control ic test mode ? ? power - on detector ? ? power supply voltage detector ? ? 7 clock calibration ? ? 80 free register access ? ?
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| real - time clock module 2 015 - 12 - 000 1 pt0 280 - 8 12 / 11 /1 5 2 pt7c43390 /43390c pin configuration pin description pin no. pin name type description 43390 43390c 1 1 int 1 o output for interrupt signal 1 . this pin outputs a signal of interrupt, or a clock pulse . by using the status register 2, users can select either of : alarm 1 interrupt, output of user - set frequency, per - minut e edge interrupt, minute - periodical interrupt 1 , m inute - periodical interrupt 2, or 32. 768 khz output. this pin has n ch open drain output. 2 - x out o oscillator circuit output. together with x1, 32.768khz crystal is connected between them. when 32.768khz e xternal input, x2 must be float. - 2 nc1 - n o connected. 3 - x in i oscillator circuit input. together with x1, 32.768khz crystal is connected between them. or external clock input. - 3 nc2 - n o connected. 4 4 vss p negative power supply pin . connects t o gnd. 5 5 int 2 o output for interrupt signal 2 . this pin outputs a signal of interrupt, or a clock pulse. by using the status register 2, user s can select either of : alarm2 interrupt, output of user - set frequency, or minute - periodic al interrupt 1. this pin has n ch open drain output. 6 6 sc l i serial clock input pin . this pin is to input a clock pulse for i 2 c - bus interface. the sda pin inputs/ outputs data by synchronizing with the clock pulse. 7 7 sda i/o serial data input/output. this is a data input / output pin of i 2 c - bus interface. this pin inputs / outputs data by s ynchronizing with a clock pulse from the scl pin. this pin has cmos input and n ch open drain output. generally in u se, pull up this pin to the v dd potential via a resistor, and connect i t to any other device having open drain or open collector output wi th wired - or connection. 8 8 vdd p positive power supply pin . connect this vdd pin with a positive power supply. 1 2 3 i n t 1 4 p t 7 c 4 3 3 9 0 s o i c - 8 l x i n x o u t g n d 8 7 6 5 i n t 2 s c l s d a v d d 1 i n t 1 p t 7 c 4 3 3 9 0 c t d f n 4 x 4 - 8 l n c 2 n c 1 g n d i n t 2 s c l s d a v d d 4 2 3 8 5 7 6 g n d p 2 p 1 i n t 1 4 p t 7 c 4 3 3 9 0 t s s o p - 8 l x i n x o u t g n d i n t 2 s c l s d a v d d 3 2 1 5 6 7 8 i n t 1 p t 7 c 4 3 3 9 0 t d f n 2 x 3 - 8 l x i n x o u t g n d i n t 2 s c l s d a v d d 2 1 4 3 7 8 5 6
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||| ||||||||| 2 015 - 12 - 000 1 pt0 280 - 8 12 / 11 /1 5 3 p t7c43390 /43390c real - time clock module block diagram s e c o n d o s c i l l a t o r d i v i d e r , t i m i n g g e n e r a t o r i n t r e g i s t e r 1 i n t c o n t r o l l e r 1 c l o c k c o r r e c t i o n r e g i s t e r s t a t u s r e g i s t e r 1 s t a t u s r e g i s t e r 2 f r e e r e g i s t e r l o w p o w e r s u p p l y v o l t a g e d e t e c t o r p o w e r - o n d e t e c t i o n c i r c u i t c o n s t a n t - v o l t a g e c i r c u i t c o m p a r a t o r 1 m i n u t e h o u r d a y o f w e e k d a y m o n t h y e a r c o m p a r a t o r 2 r e a l - t i m e d a t a r e g i s t e r i n t r e g i s t e r 2 i n t c o n t r o l l e r 2 i n t r e g i s t e r 2 s e r i a l i n t e r f a c e s d a s c l i n t 1 v s s v d d x o u t x i n p t 7 c 4 3 3 9 0 i n t 2 s e c o n d o s c i l l a t o r d i v i d e r , t i m i n g g e n e r a t o r i n t r e g i s t e r 1 i n t c o n t r o l l e r 1 c l o c k c o r r e c t i o n r e g i s t e r s t a t u s r e g i s t e r 1 s t a t u s r e g i s t e r 2 f r e e r e g i s t e r l o w p o w e r s u p p l y v o l t a g e d e t e c t o r p o w e r - o n d e t e c t i o n c i r c u i t c o n s t a n t - v o l t a g e c i r c u i t c o m p a r a t o r 1 m i n u t e h o u r d a y o f w e e k d a y m o n t h y e a r c o m p a r a t o r 2 r e a l - t i m e d a t a r e g i s t e r i n t r e g i s t e r 2 i n t c o n t r o l l e r 2 i n t r e g i s t e r 2 s e r i a l i n t e r f a c e s d a s c l i n t 1 v s s v d d x o u t x i n p t 7 c 4 3 3 9 0 c i n t 2 c d c g 3 2 . 7 6 8 k h z
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||| ||||||||| 2 015 - 12 - 000 1 pt0 280 - 8 12 / 11 /1 5 4 p t7c43390 /43390c real - time clock module maximum ratings storage temperature ................................ ................................ .................... - 5 5 o c to +1 25 o c operating temperature ................................ ................................ .................. - 40 o c to +85 o c power supply voltage ................................ ................................ ........ vss - 0. 3 v to vss + 6.5 v dc input voltage (scl, sda ) ................................ ......................... vss - 0.3v to vss + 6.5v dc out put voltage (sda, int 1, int2 ) ................................ ....... vss - 0.3v to vss + 6.5v power d issipation ................................ .......................... 25 0 m w (depend on package) recommended operating conditions symbol parameter conditions min t yp max unit v dd power supply voltage t a = ?40 to +85c 1.3 5 3.0 5.5 v t opr operating temperature v dd =1.3 to 5.5 v ? 40 +25 +85 c v ddt time keeping voltage range t a = ?40 to +85c 1.25 - 5.5 v v ddr register hold voltage t a = ?40 to +85c 0.9 - 5.5 v v d e t power supply voltage detection volta ge * 1 t a = ?40 to +85c 0.70 1.05 1.40 v c l crystal oscillator c l value - - 6 12.5 pf *1. power supply voltage detection voltage: constantly maintains the relation of v det > v dd rm (minimum data hold voltage). oscillation characteristics ( for pt7c43390 : t a = 25c, v dd = 3.0 v, v ss = 0 v, crystal oscillator (c l = 6 pf, 32.768 khz).) symbol parameter conditions min. typ. max. unit v sta oscillation start voltage within 10 seconds 1.1 - 5.5 v - oscillation start time - - - 3 s ic ic to ic frequency devia tion - - 10 - +10 ppm v frequency voltage deviation v dd =1.3 5 to 5.5 v - 3 - +3 ppm ( for pt7c43390c: t a = 25c, v dd = 3.0 v, v ss = 0 v .) symbol parameter conditions min. typ. max. unit v sta oscillation start voltage within 10 seconds 1.1 - 5.5 v - osc illation start time - - - 3 s ic ic to ic frequency deviation - - 10 - +10 ppm ? f / f frequency tolerance - - 30 - + 30 ppm v frequency voltage deviation vdd =1.3 to 5.5 v - 3 +3 ppm fa aging f irst year 5 ppm/year stresses greater than those listed under maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specifi cation is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability.
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||| ||||||||| 2 015 - 12 - 000 1 pt0 280 - 8 12 / 11 /1 5 5 p t7c43390 /43390c real - time clock module dc electrical characteristics ( t a = - 40 c to +85 c ; v ss = 0 v, crystal oscillator c l = 6 pf, 32.768khz , unless otherwise noted. ) symbol parameter pin test conditions min typ max unit v dd = 3.0v i dd1 current consumption 1 v dd out of communication - 0.3 0.6 a i dd2 current consumption 2 v dd during communication (scl =100khz) - 3.5 8 a i izh input high leakage current scl,sda v in = v dd - 0.5 - +0.5 a i izl input low leakage current scl,sda v in = v ss - 0.5 - +0.5 a i ozh output high leakage current sda,int1, int2 v out = v dd - 0.5 - +0.5 a i ozl output low leakage current sda,int1, int2 v out = v ss - 0.5 - +0.5 a v ih input high voltage scl,sda - 0.8v dd - - v v il input low voltage scl,sda - - - 0.2v dd v i ol1 output low current 1 int 1 v out = 0.4v 1.0 1.6 - ma int2 v out = 0.4v 5 8 - ma i o l 2 output low current 2 s da v out = 0.4v 5 8 - ma v dd = 5.0v i dd1 current consumption 1 v dd out of communication - 0. 3 5 0. 7 a i dd2 current consumption 2 v dd during communication (sck=100khz) - 7 14 a i izh input high leakage current scl,sda v in = v dd - 0.5 - +0.5 a i izl input low leakage current scl,sda v in = v ss - 0.5 - +0.5 a i ozh output high leakage current sda,int1, int2 v out = v dd - 0.5 - +0.5 a i ozl output low leakage current sda,int1, int2 v out = v ss - 0.5 - +0.5 a v ih input high voltage scl ,sda - 0.8v dd - - v v il input low voltage scl,sda - - - 0.2v dd v i ol1 output low current 1 int 1 v out = 0.4v 1.0 1.6 - ma int2 6 10 - ma i ol 2 output low current 2 s da v out = 0.4v 6 10 - ma
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||| ||||||||| 2 015 - 12 - 000 1 pt0 280 - 8 12 / 11 /1 5 6 p t7c43390 /43390c real - time clock module a c electrical characteristics measure condi tions input pulse voltage v ih = 0.9 v dd , v il = 0.1 v dd input pulse rise/fall time 20ns output determination voltage v oh = 0.5 v dd , v ol = 0.5 v dd output load 100pf + pull - up resistance 1 k symbol parameter v dd > 1.3 5 v *2 v dd > 3.0 v *2 un it min. typ. max. min. typ. max. f scl scl clock frequency 0 - 100 0 - 400 khz t low scl clock low time 4.7 - - 1.3 - - s t high scl clock high time 4 - - 0.6 - - s t pd sda output delay time - - 3.5 - - 0.9 s t su.sta start condition setup time 4.7 - - 0.6 - - s t hd.sta start condition hold time 4 - - 0.6 - - s t su.dat data input setup time 250 - - 100 - - ns t hd.dat data output hold time 0 - - 0 - - s t su.sto stop condition setup time 4.7 - - 0.6 - - s t r scl, sda rise time - - 1 - - 0.3 s t f scl, sda fall time - - 0.3 - - 0.3 s t buf bus release time 4.7 - - 1.3 - - s t i noise suppression time - - 100 - - 50 ns *1. si nce the output format of the sda pin is nch open - drain output, output data definition time is determined by the values of the load resistance (r l ) and load capacity (c l ) outside the ic. therefore, use this value only as a reference value. *2 regarding the power supply voltage, refer to recommended operating conditions .
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||| ||||||||| 2 015 - 12 - 000 1 pt0 280 - 8 12 / 11 /1 5 7 p t7c43390 /43390c real - time clock module recommended layout for crystal (for pt7c43390) b uilt - in capacitors specifications and recommended external capacitors parameter symbol typ. unit build in capacitors xin to gnd c g 5 pf xout to gnd c d 5 pf recommended external capacitors for crystal c l =12.5pf xin to gnd c1 18 pf xout to gnd c2 18 p f recommended external capacitors for crystal c l =6pf xin to gnd c1 7 pf xout to gnd c2 7 pf note : the frequency of crystal can be optimized by external capacitor c1 and c2, for frequency=32 . 768 k hz, c1 and c2 should meet the equation as below: cpar + [ (c1+c g )*(c2+c d )]/ [(c1+c g ) + (c2+c d )] =c l cpar is all parasitical capacitor between x1 and x2. c l is crystals load capacitance. crystal specifications parameter symbol min. typ. max. unit nominal frequency f o - 32.768 - khz serial resistance esr - - 70 k load capacitance c l - 6/12.5 - pf
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||| ||||||||| 2 015 - 12 - 000 1 pt0 280 - 8 12 / 11 /1 5 8 p t7c43390 /43390c real - time clock module functional description 1. overview of functions 1.1. clock function cpu can read or write data including the year (last two digits), month, date, day, hour, minute, and second. any (two - digit) year that is a multiple o f 4 is treated as a leap year and calculated automatically as such until the year 2099. 1.2. alarm function this device has two alarm system (alarm 1 and alarm 2) that outputs interrupt signals from int1 pin or int2 pin to cpu when the date, day of the week, hour, minute or second correspond to the setting. each of them may output interrupt signal separately at a specified time. the alarm may be selectable between on and off for matching alarm or repeating alarm. 1.3. programmable square wave output for pt7c43 3 9 0, square wave output at pin 1 or pin 5 . six frequencies are selectable: 1, 2, 4, 8, 16, 32768 hz. 1.4. interface with cpu pt7c43 3 90: i 2 c bus interface . 1.5. calibration function with the calibration bits properly set, the accuracy can be improved to better than 2 ppm at 25c. 2. con figuration of data communication 2.1. data communication for data communication, the master device in the system generates a start condition for the ic. next, the master devices tran smits 4 - bit device code 0110, 3 - bit command and 1 - bi t read / write command to the sda line. after that, output or input is performed from b7 of data. if data i/o has been completed, finish communication by inputting a stop condition to the ic. the master dev ice generates an acknowledgment signal for every 1 - byte. regarding details refer to " i 2 c - bus serial interface ". 0 d e v i c e c o d e c o m m a n d 1 1 0 c 2 c 1 c 0 r / w b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 1 - b y t e d a t a r e a d / w r i t e b i t s t a s t a r t c o n d i t i o n a c k a c k n o w l e d g m e n t b i t a c k s t o p c o n d i t i o n s t p
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||| ||||||||| 2 015 - 12 - 000 1 pt0 280 - 8 12 / 11 /1 5 9 p t7c43390 /43390c real - time clock module 2.2. configuration of command 8 types of command are available for the rtc. the rtc reads / writes the various registers by inputting these fixed codes and commands. th e rtc does not perform any operation with any codes and commands other than those below. however, in case that the fixed codes or the commands are failed to be recognized in the 1st byte but are successfully recognized in the 2nd and hi gher bytes, the comm ands are executed. *1. write only flag. the pt7c43390 initializes by writing "1" in this register. *2. scratch bit. this is a register which is available for read / write operations and can be used by users freely. *3. read only flag. valid only when us e the alarm function. when the alarm time matches, this flag is set to "1", and it is cleared to "0" when reading. *4. read only flag. "poc" is set to "1" when power is applied. it is cleared to "0" when reading. regarding "bld", refer to " low power supply voltage detection circuit ". *5. test bit. be sure to set "0" in use. *6. no effect when writing. it is "0" when reading. 3. configuration of registers 3.1. real - time data register the real - time data register is a 7 - byte register that stores the data of year, m onth, day, day of the week, hour, minute, and second in the bcd code. to write / read real - time data 1 access, transmit / receive the data of year in b7, month, day, day of the week, hour, minute, second in b0, in 7 - byte. when you skip the procedure to acc ess the data of year, month, day, day of the week, read / write real - time data 2 accesses. in this case, transmit / receive the data of hour in b7, minute, second in b0, in 3 - byte. the rtc transfers a set of data of time to the real - time data register when it recognizes the read command. therefore, the rtc keeps precise time even if time - carry occurs during the read operation of real - time data register.
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||| ||||||||| 2 015 - 12 - 000 1 pt0 280 - 8 12 / 11 /1 5 10 p t7c43390 /43390c real - time clock module year data (00 to 99): y1, y2, y4, y8, y10, y20, y40, y80 sets the lower two digits of the western calen dar year (00 to 99) and links together with the auto calendar function until 2099. example: 2053 (y1, y2, y4, y8, y10, y20, y40, y80) = (1, 1, 0, 0, 1, 0, 1, 0) month data (01 to 12): m1, m2, m4, m8, m10 example: december (m1, m2, m4, m8, m10, 0, 0, 0) = ( 0, 1, 0, 0, 1, 0, 0, 0) day data (01 to 31): d1, d2, d4, d8, d10, d20 the count value is automatically changed by the auto calendar function. 1 to 31: jan., mar., may, july, aug., oct., dec., 1 to 30: april, june, sep., nov. 1 to 29: feb. (leap year), 1 to 28: feb. (non - leap year) example: 29 (d1, d2, d4, d8, d10, d20, 0, 0) = (1, 0, 0, 1, 0, 1, 0, 0) day of the week data (00 to 06): w1, w2, w4 day of the week is counted in the order of 00, 01, 02, 03, 04, 05, 06, and 00. set up day of the week and the coun t value. hour data (00 to 23 or 00 to 11): h1, h2, h4, h8, h10, h20, am / pm in 12 - hour mode, write 0; am, 1; pm in the am / pm bit. in 24 - hour mode, users can write either 0 or 1. 0 is read when the hour data is from 00 to 11, and 1 is read when from 12 t o 23. example (12 - hour mode): 11 p.m. (h1, h2, h4, h8, h10, h20, am / pm, 0) = (1, 0, 0, 0, 1, 0, 1, 0) example (24 - hour mode): 22 (h1, h2, h4, h8, h10, h20, am / pm, 0) = (0, 1, 0, 0, 0, 1, 1, 0)
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||| ||||||||| 2 015 - 12 - 000 1 pt0 280 - 8 12 / 11 /1 5 11 p t7c43390 /43390c real - time clock module minute data (00 to 59): m1, m2, m4, m8, m10, m20, m40 examp le: 32 minutes (m1, m2, m4, m8, m10, m20, m40, 0) = (0, 1, 0, 0, 1, 1, 0, 0) example: 55 minutes (m1, m2, m4, m8, m10, m20, m40, 0) = (1, 0, 1, 0, 1, 0, 1, 0) second data (00 to 59): s1, s2, s4, s8, s10, s20, s40 example: 19 seconds (s1, s2, s4, s8, s10, s 20, s40, 0) = (1, 0, 0, 1, 1, 0, 0, 0) 3.2. status register 1 status register 1 is a 1 - byte register that is used to display and set various modes. the bit configuration is shown below. b1: bld this flag is set to "1" when the power supply voltage decreases to the level of detection voltage (vdet) or less. users can detect a drop in the power supply voltage. this flag is set to "1" once, is not set to "0" again even if the power supply increases to the level of detection voltage (vdet) or more. this flag is r ead - only. when this flag is "1", be sure to initialize. regarding the operation of the power supply voltage detection circuit, refer to " low power supply voltage detection circuit ". b2: int2, b3: int1 this flag indicates the time set by alarm and when the time has reached it. this flag is set to "1" when the time that users set by using the alarm interrupt function has come. the int1 flag at alarm 1 interrupt mode and the int2 flag at alarm 2 interrupt m ode are set to "1". set "0" in int1ae (b5 in the statu s register 2) or in int2ae (b1 in the status register 2) after reading "1" in the int1 flag or in the int2 flag. this flag is read - only. this flag is read once, is set to "0" automatically. b4: sc1, b5: sc0 these flags are sram type registers, they are 2 b its as a whole, can be freely set by users. b6: 12 / 24 this flag is used to set 12 - hour or 24 - hour mode. set the flag ahead of write operation of the real - time data register in case of 24 - hour mode. 0: 12 - hour mode 1: 24 - hour mode b7: reset the internal i c is initialized by setting this bit to "1". this bit is write - only. it is always "0" when reading. when applying the power supply voltage to the ic, be sure to write "1" to this bit to initialize the circuit. regarding each status of data aft er initializa tion, refer to " register status after initialization ". 3.3. status register 2 status register 2 is a 1 - byte register that is used to display and set various modes. the bit configuration is shown below. b0: test this is a test flag. be sure to set this flag to "0" in use. if this flag is set to "1", be sure to initialize to set "0". b1: int2ae, b2: int2me, b3: int2fe these bits are used to select the output mode for the int2 pin. below table shows how to select the mode. to use an alarm 2 interrupt, set alarm interrupt mode, then access the int2 register. table: output modes for int2 pin i n t 1 f e i n t 1 m e i n t 1 a e 3 2 k e i n t 2 f e i n t 2 m e i n t 2 a e t e s t b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 r / w r / w r / w r / w r / w r / w r / w r / w r / w : r e a d / w r i t e
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||| ||||||||| 2 015 - 12 - 000 1 pt0 280 - 8 12 / 11 /1 5 12 p t7c43390 /43390c real - time clock module *1. don't care (both of 0 and 1 are acceptable). b4: 32ke, b5: int1ae, b6: int1me, b7: int1fe these bits are used to select the output mode for the int1 pin. below table shows how to select the mode. to use alarm 1 interrupt, access the int1 register after setting the alarm interrupt mode. table: output modes for int1 pin *1. don't care (both of 0 and 1 are acceptable ). 3.4. int register 1 and int register 2 the int1 and int2 registers are to set up the output of user - set frequency, or to set up alarm interrupt. users are able to switch the output mode by using the status register 2. if selecting to use the output mode fo r alarm interrupts by status register 2; these registers work as alarm - time data registers. if selecting the output of user - set frequency by status register 2; these registers work as data registers to set the frequency for clock output. from each int1 and int2 pin, a clock pulse and alarm interrupt are output. a. alarm interrupt users can set the alarm time (the data of day of the week, hour, minute) by using the int1 and int2 registers which are 3 - byte data registers. the configuration of register is as wel l as the data register of day of the week, hour, minute, in the real - time data register; is expressed by the bcd code. do not set a nonexistent day. users are necessary to set up the alarm - time data according to the 12 / 24 hour mode that they set by using the status register 1. int register 1 and int register 2 (alarm - time data) the int register 1 has a1we, a1he, and a1me at b0 in each byte. it is possible to make data valid; the data of day of the wee k, hour, minute which are in the corresponded byte; by setting these bits to "1". this is as well in a2we, a2he, and a2me in the int register 2. setting example: alarm time "7:00 pm" in the int register 1
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||| ||||||||| 2 015 - 12 - 000 1 pt0 280 - 8 12 / 11 /1 5 13 p t7c43390 /43390c real - time clock module (1) 12 - hour mode (status register 1 b6 = 0) set up 7:00 pm data written to int register 1 *1. don't care (both of 0 and 1 are acceptable). (2) 24 - hour mode (status register 1 b6 = 1) set up 19:00 pm data written to int register 1 *1. don't care (both of 0 and 1 are acceptable). *2 . set up am / pm fl ag along with the time setting. b. int register 1 and int register 2 ? output of user - set frequency the int1 and int2 registers are 1 - byte data registers to set up the output frequency. setting each bit b7 to b3 in the register to "1", the frequency which corr esponds to the bit is output in the and - form. sc2 to sc4 in the int1 register, and sc5 to sc7 in the int2 register are 3 - bit sram type registers that can be freely set by users. int register 1 (data register for output frequenc y) int register 2 (data register for output frequency) _ ( * 1 ) 0 1 1 1 0 0 0 1 1 0 0 0 0 0 0 0 1 b 7 b 0 d a y o f t h e w e e k h o u r m i n u t e _ ( * 1 ) _ ( * 1 ) _ ( * 1 ) _ ( * 1 ) _ ( * 1 ) _ ( * 1 ) 0 1 0 0 1 1 0 1 ( * 2 ) 1 0 0 0 0 0 0 0 1 b 7 b 0 d a y o f t h e w e e k h o u r m i n u t e _ ( * 1 ) _ ( * 1 ) _ ( * 1 ) _ ( * 1 ) _ ( * 1 ) _ ( * 1 ) _ ( * 1 ) 1 h z 2 h z 4 h z 8 h z 1 6 h z s c 2 s c 3 s c 4 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 r / w r / w r / w r / w r / w r / w r / w r / w r / w : r e a d / w r i t e 1 h z 2 h z 4 h z 8 h z 1 6 h z s c 5 s c 6 s c 7 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 r / w r / w r / w r / w r / w r / w r / w r / w r / w : r e a d / w r i t e
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||| ||||||||| 2 015 - 12 - 000 1 pt0 280 - 8 12 / 11 /1 5 14 p t7c43390 /43390c real - time clock module example of output from int1 and int2 registers (data register for output frequency) 3.5. clock correction register the clock correction register is a 1 - byte register that is used to correct advance / delay of the clock. when not using this function, set this register to "00h". regarding the register values, refer to " function to clock correction ". 3.6. free register this free register is a 1 - byte sram t ype register that can be set freely by users. 4. power - on detection circuit and register status the power - on detection circuit operates by power - on the rtc, as a result each register is cleared; each register is set as follows. r eal - time data register: 00 (y), 01 (m), 01 (d), 0 (day of the week), 00 (h), 00 (m), 00 (s) status register 1: "01h" status register 2: "80h" int register 1: "80h" int register 2: "00h" clock correction register: "00h" free register: "00h" "1" is set in th e poc flag (b0 in the status register 1) to indicate that power has been applied. to correct the oscillation frequency, the status register 2 goes in the mode the output of user - set frequency, so that 1 hz clock pulse is output from the int pin. when "1" i s set in the poc flag, be sure to initialize. the poc flag is set to "0" due to initialization so that the output of user - set frequency mode is cleared. (refer to " register status after initialization ".) v 0 v 1 v 2 v 3 v 4 v 5 v 6 v 7 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 r / w r / w r / w r / w r / w r / w r / w r / w r / w : r e a d / w r i t e
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||| ||||||||| 2 015 - 12 - 000 1 pt0 280 - 8 12 / 11 /1 5 15 p t7c43390 /43390c real - time clock module for the regular operation of power - on detection circ uit, as seen in below figure , the period to power - up the rtc is that the voltage reaches 1.3 v within 10 ms after setting the ics power supply voltage at 0 v. when the power - on detection circuit is not working normally is; the poc flag (b0 in the status r egister) is not in "1", or 1 hz is not output from the int pin. in this case, power - on the rtc once again because the internal data may be in the indefinite status. moreover, regarding the processing right after power - on, refer to " flowchart of initializat ion and example of real - time data set - up " . *1. 0 v indicates that there are no potential differences between the vdd pin and vss pin. how to raise the power supply voltage 5. register status after initialization the status of each register after initializa tion is as follows. real - time data register: 00 (y), 01 (m), 01 (d), 0 (day of the week), 00 (h), 00 (m), 00 (s) status register 1: "0 b6 b5 b4 0 0 0 0 b" (in b6, b5, b4, the data of b6, b5, b6 in the status register 1 at initialization is set. refer to be low figure .) status register 2: "00h" int1 register: "00h" int2 register: "00h" clock correction register: "00h" free register: "00h" ? status register 1 data at initialization
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||| ||||||||| 2 015 - 12 - 000 1 pt0 280 - 8 12 / 11 /1 5 16 p t7c43390 /43390c real - time clock module 6. low power supply voltage detection circuit the rtc has a low power sup ply voltage detection circuit, so that users can monitor drops in the power supply voltage by reading the bld flag (b1 in the status register 1). there is a hysteresis width of approx. 0.15 v (typ.) between detection voltage an d release voltage (refer to " characteristics (typical data) "). the low power supply voltage detection circuit does the sampling operation only once in one sec for 15.6 ms. if the power supply voltage decreases to the level of detection voltage (vdet) or less, "1" is set to the bld fla g so that sampling operation stops. once "1" is detected in the bld flag, no sampling operation is performed even if the power supply voltage increases to the level of release voltage or more, and "1" is held in the bld flag . if the bld flag is "1" even af ter the power supply voltage is recovered, the internal circuit may be in the indefinite status. in this case, be sure to initialize the circuit. after reading the bld flag, the sampling operation is restarted. without initializing, if the next bld flag re ading is done after sampling, the bld flag gets reset to "0". in this case, be sure to initialize although the bld flag is in "0" because the internal circuit may be in the indefinite status. timing of low power supply voltage detection circuit 7. circuit s power - on and low power supply voltage detection below figure shows the changes of the poc flag and bld flag due to vdd fluctuation. poc flag and bld flag
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||| ||||||||| 2 015 - 12 - 000 1 pt0 280 - 8 12 / 11 /1 5 17 p t7c43390 /43390c real - time clock module 8. nonexistent data and end - of - month when users write the real - time data, the rtc checks it. in case that the data is invalid, the rtc does the following procedures. ? processing of nonexistent data *1. in 12 - hour mode, write the am / pm flag (b1 in hour data in the real - time data register). in 24 - hour expression, the am / pm flag in the real - time data register is omitted. however in the flag of reading, users are able to read 0; 0 to 11, 1; 12 to 23. *2. processing of nonexistent data, regarding second data, is done by a carry pulse which is generated in 1 second, after writing . at this point the carry pulse is sent to the minute - counter. ? correction of end - of - month a nonexistent day, such as february 30 and april 31, is set to the first day of the next month. 9. alarm and interrupt output 9.1. int1 pin and int2 pin output mode these are selectable f or the output mode for int1 and int2 pins; alarm interrupt, the output of user - set frequency, per - minute edge interrupt output, minute - periodical interrupt output 1. in the int1 pin output mode, in addition to the above modes, minute - periodical interrupt o utput 2 and 32.768 khz output are also selectable. to switch the output mode, use the status register 2. refer to " status register 2 " in " configuration of registers ". when switching the output mode, be careful of the output status of the pin. especially, w hen using alarm interrupt / output of frequency, switch the output mode after setting "00h" in the int1 / int2 register. in 32.768 khz output / per - minute edge interrupt output / minute - periodical interrupt output, it is unnecessary to set data in the int1 / int2 register for users. refer to the followings regarding each operation of output modes. a. alarm interrupt output alarm interrupt output is the function to output "l" from the int1 / int2 pin, at the alarm time which is set by user has com e. if setting the pin output to "h", turn off the alarm function by setting "0" in int1ae / int2ae in the status register 2. to set the alarm time, set the data of day of the week, hour and minute in the int1 / int2 register. refer to " int1 register and int2 register " in " configuration of registers ".
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||| ||||||||| 2 015 - 12 - 000 1 pt0 280 - 8 12 / 11 /1 5 18 p t7c43390 /43390c real - time clock module a) alarm setting of "w (day of the week), h (hour), m (minute)" *1. if users clear int1ae / int2ae once; "l" is not output from the int1 / int2 pin by setting int1ae / int2ae enable again, within a period when the alarm time matches real - time data. alarm interrupt output timing
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||| ||||||||| 2 015 - 12 - 000 1 pt0 280 - 8 12 / 11 /1 5 19 p t7c43390 /43390c real - time clock module b) alarm setting of "h (hour)" *1. if users clear int1ae / int2ae once; "l" is not output from the int1 / int2 pin by setting int1ae / int2ae enable again, within a period when the alarm time matches real - time data. *2. if turning the alarm output on by changing the program, within the period when the alarm time matches real - time data, "l" is output again from the int1 / int2 pin when the minute is counted up. alarm interrupt output timing b. outp ut of user - set frequency the output of user - set frequency is the function to output the frequency which is selected by using data, from the int1/int2 pin, in the and - form. set up the data of frequency in the int1 / int2 register. c. per - minute edge interr upt output per - minute edge interrupt output is the function to output "l" from the int1 / int2 pin, when the first minute - carry processing is done, after selecting the output mode. to set the pin output to "h", turn off the output mode of per - minute edge i nterrupt. in the int1 pin output mode, input "0" in int1me in the status register 2. in the int2 pin output mode, input "0" in int2me.
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||| ||||||||| 2 015 - 12 - 000 1 pt0 280 - 8 12 / 11 /1 5 20 p t7c43390 /43390c real - time clock module *1. pin output is set to "h" by disabling the output mode within 7.81 ms, because the signal of this procedure is maint ained for 7.81 ms. note that pin output is set to "l" by setting enable the output mode again. timing of per - minute edge interrupt output d. minute - periodical interrupt output 1 the minute - periodical interrupt 1 is the function to output the one - minute clock pulse (duty 50%) from the int1 / int2 pin, when the first minute - carry processing is done, after selecting the output mode. * 1. setting the output mode disable makes the pin output "h", while the outputs from the int1 / int2 pin is in "l". note that pi n output is set to "l" by setting enable the output mode again. timing of per - minute steady interrupt output 1 e. minute - periodical interrupt output 2 (only in the int1 pin output mode) the output of minute - periodical interrupt 2 is the function to output "l ", for 7.81 ms, from the int1 pin, synchronizing with the first minute - carry processing after selecting the output mode. however, during reading in the real - time data register, the procedure delays at 0.5 seconds max. thus output "l" from the int1 pin also delays at 0.5 seconds max. during writing in the real - time data register, some delay is made in the output period due to write timing and the second - data during writing. (1) during normal operation
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||| ||||||||| 2 015 - 12 - 000 1 pt0 280 - 8 12 / 11 /1 5 21 p t7c43390 /43390c real - time clock module (2) during reading in the real - time data register (3 ) during writing in the real - time data register timing of minute - periodical interrupt output 2 f. operation of power - on detection circuit (only in the int1 pin output mode) when power is applied to the rtc, the power - on detection operates to set "1" in th e poc flag (b0 in the status register 1). a 1 hz clock pulse is output from the int1 pin. 9.2. alarm 1 function and int2 pin output mode in the output mode for int2 pin, users are able to select the output; alarm 2 interrupt, user - set frequency, per - minute ed ge interrupt, minute - periodical interrupt. to switch the output mode for int2 pin and the alarm 1 function, use the status register 2. refer to " status register 2 " in " configuration of registers ". when switching the output mode for int2 pin, be careful of the output status of the pin. especially, when using alarm 2 interrupt output, or the output of user - set frequency, switch the output mode after setting "00h" in the int2 register. in per - minute edge interrupt output / minute - periodical interrupt output, i t is unnecessary to set data in the int2 register for users. refer to the followings regarding each operation of output modes.
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||| ||||||||| 2 015 - 12 - 000 1 pt0 280 - 8 12 / 11 /1 5 22 p t7c43390 /43390c real - time clock module a. alarm 1 function and alarm 2 interrupt alarm 2 interrupt output is the function to set the int2 flag "h" by the output "l" from the int2 pin, at the alarm time which is set by user has come. if setting the pin output to "h", turn off the alarm function by setting "0" in int2ae in the status re gister 2. by reading, the int2 flag is once cleared automatically. in the alarm 1 function , the int1 flag (b3 in the status register 1) is set to "h" when the set time has come. the int1 flag is also cleared once by reading. in the alarm 1 function, set the data of day o f the week, hour, minute of the alarm time in the int1 register. in alarm 2 interrupt, set in the int2 register. 1) alarm setting of "w (day of the week), h (hour), m (minute)" *1. if users clear int2ae once; "l" is not output from the int2 pin by setting int2ae enable again, within a period when the alarm time matches real - time data. alarm interrupt output timing
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||| ||||||||| 2 015 - 12 - 000 1 pt0 280 - 8 12 / 11 /1 5 23 p t7c43390 /43390c real - time clock module 2) alarm setting of "h (hour)" *1. if users clear int2ae once; "l" is not output from the int2 pin by setting int2ae enable again, within a period when the alarm time matches real - time data. *2. if turning the alarm output on by changing the program, within the period when the alarm time matches real - time data, "l" is output again from the int2 pin when the minute is counted up. alarm interrupt output timing b. output of user - set frequency the output of user - set f requency is the function to output the frequency which is selected by using data, from the int2 pin, in the and - form. set up the data of frequency in the int2 register. refer to " int1 register and int2 register " in " configuration of registers ". output ti ming of user - set frequency c. per - minute edge interrupt output per - minute edge interrupt output is the function to output "l" from the int2 pin, when the first minute - carry processing is done, after selecting the output mode. to set the pin output to "h", in the int2 pin output mode, input "0" in int2me in the status register 2 in order to turn off this mode.
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||| ||||||||| 2 015 - 12 - 000 1 pt0 280 - 8 12 / 11 /1 5 24 p t7c43390 /43390c real - time clock module *1. pin output is set to "h" by disabling the output mode within 7.81 ms, because the signal of this procedure is maintained for 7.81 ms. note that pi n output is set to "l" by setting enable the output mode again. timing of per - minute edge interrupt output d. minute - periodical interrupt output 1 the minute - periodical interrupt 1 is the function to output the one - minute clock pulse (duty 50%) from the int2 pin, when the first minute - carry processing is done, after selecting the output mode. *1. setting the output mode disable makes the pin output "h", while the output from the int2 pin is in "l". note that pin output is set to "l" by setting enable the ou tput mode again. timing of minute - periodical interrupt output 1 10. function to clock correction the function to clock correction is to correct advance / delay of the clock due to the deviation of oscillation frequency, in order to make a high precise clock. for correction, the rtc adjusts the clock pulse by using a certain part of the dividing circuit, not adjusting the frequency of the crystal oscillator. correction is performed once every 20 seconds (or 60 seconds). the minimum resolution is approx. 3 ppm ( data, refer to " 15.2. how to calcu late ". when not using this function, be sure to set "00h". function to clock correction
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||| ||||||||| 2 015 - 12 - 000 1 pt0 280 - 8 12 / 11 /1 5 25 p t7c43390 /43390c real - time clock module 10.1. setting values for registers and correction values setting values for registers and correction values (minimum resolution: 3.052 ppm (b0 = 0)) setting values for registers and correction values (minimum resolution: 1.017 ppm (b0 = 1))
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||| ||||||||| 2 015 - 12 - 000 1 pt0 280 - 8 12 / 11 /1 5 26 p t7c43390 /43390c real - time clock module 10.2. how to calculate a. if current oscillation frequency > target frequency (in case the clock is fast) caution the figure range which can be corrected is that the calculated va lue is from 0 to 64. *1. convert this value to be set in the clock correction register. for how to convert, refer to " calculation example 1 " . *2. measurement value when 1 hz clock pulse is output from the int pin. *3. target value of average frequency whe n the clock correction function is used. *4. refer to " function to clock correction ". ? calculation example 1 in case of current oscillation frequency actual measurement value = 1.000070 [hz], target oscillation frequency = 1.000000 [h z], b0 = 0 (minimum re solution = 3.052 ppm) convert the correction value "106" to 7 - bit binary and obtain "1101010b". reverse the correction value "1101010b" and set it to b7 to b1 of the clock correction register. thus, set the clock correction register: (b7, b6, b5, b4, b3 , b2, b1, b0) = (0, 1, 0, 1, 0, 1, 1, 0) b. if current oscillation frequency < target frequency (in case the clock is fast) caution the figure range which can be corrected is that the calculated value is from 0 to 62. ? calculation example 2 in case of curr ent oscillation frequency actual measurement value = 0.999920 [hz], target oscillation frequency = 1.000000 [hz]. b0 = 0 (minimum resolution = 3.052 ppm) thus, set the clock correction register: (b7, b6, b5, b4, b3, b2, b1, b0) = (1, 1, 0, 1, 1, 0, 0, 0) ? calculation example 3 in case of current oscillation frequency actual measurement value = 0.999920 [hz], target oscillation frequency = 1.000000 [h z], b0 = 1 (minimum resolution = 1.017 ppm) this calculated value exceeds the correctable range 0 to 62. b0 = "1" (minimum resolution = 1.017 ppm) indicates the correction is impossible.
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||| ||||||||| 2 015 - 12 - 000 1 pt0 280 - 8 12 / 11 /1 5 27 p t7c43390 /43390c real - time clock module 10.3. how to confirm a setting value for a register and the result of correction this rtc does not adjust the frequency of the crystal oscillation by using the function of cloc k correction. therefore users cannot confirm if it is corrected or not by measuring output 32.768 khz. when the function of clock correction is being used, the cy cle of 1 hz clock pulse output from the int pin changes once in 20 times or 60 times, as shown in below figure. confirmation of the clock correction measure a and b by using the frequency counter *1 . calculate the average frequency (tave) based on the measurement results. calculate the error of the clock based on the average frequency (tave). the following shows an example for confirmation. confirmation example: when b0 =0, 66h is set measurement results: a = 1.000080 hz, b = 0.998493 hz calculating the average frequency allows to confirm the result of correction. *1. use a high - accuracy frequency counter of 7 digits or more. caution measure the oscillation frequency under the usage conditions. 11. serial interface 11.1. i 2 c - bus serial interface a. start condition a start condition is when the sda line changes "h" to "l" when the scl line is in "h", so that the access starts. b. stop condition a stop condition is when the sda line changes "l" to "h" when the scl line is in "h", and the access stops, so that the pt7c43390 gets standby. start / s top conditions c. data transfer and acknowledgment signal data transmission is performed for every 1 - byte, after detecting a start condition. transmit data while the scl line is in "l", and be careful of spec of tsu.dat and thd. dat when changing the sda line . if the sda line changes while the scl line is in "h", the data will be recognized as start/stop condition in spite of data transmission. note that by this case, the access will be interrupted. during data transmission, every moment receiving 1 - byte data, the devices which work for receiving data send an
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||| ||||||||| 2 015 - 12 - 000 1 pt0 280 - 8 12 / 11 /1 5 28 p t7c43390 /43390c real - time clock module acknowledgment signal back. for example, as seen in below figure , in case that the pt7c43390 is the device working for receiving data and the master device is the one working for sending data; when the 8th clock pulse falls, the master device releases the sda line. after that, the pt7c43390 sends an acknowledgment signal back, and set the sda line to "l" at the 9th clock pul se. the pt7c43390 does not output an acknowledgment signal is that the access is not being done regularly. output timing of acknowledgment signal ? data reading in the pt7c43390 after detecting a start condition, the pt7c43390 receives device code and command. the pt7c43390 enters the read - data mode by the read / write bit "1". the data is output from b7 in 1 - byte. input an acknowledgment signal from the master device every moment that the pt7c43390 outputs 1 - byte data. however, do not input an acknowledgment signal (input no_ack) for the last data - byte output from the master device. this procedure notifies the completion of reading. next, input a stop condition to the pt7c43390 to finish access. example of data reading 1 (1 - byte data register)
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||| ||||||||| 2 015 - 12 - 000 1 pt0 280 - 8 12 / 11 /1 5 29 p t7c43390 /43390c real - time clock module example of data reading 2 (3 - byte data register) ? data writing in the pt7c43390 after detec ting a start condition, the pt7c43390 receives device code and command. the pt7c43390 enters the write - data mode by the read / write bit "0". input data from b7 to b0 in 1 - byte. the pt7c43390 outputs an acknowledgment signal "l" every moment that 1 - byte da ta is input. after receiving the acknowledgment signal which is for the last byte - data, input a stop condition to the pt7c43390 to finish access. example of data writing 1 (1 - byte data register) example of data reading 2 (3 - byte data register)
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||| ||||||||| 2 015 - 12 - 000 1 pt0 280 - 8 12 / 11 /1 5 30 p t7c43390 /43390c real - time clock module d. data access ? real - time data 1 access *1. set no_ack = 1 when reading. *2. transmit ack = 0 from the master device to the rtc when reading. real - time data 1 access ? real - time data 2 access *1. set no_ack = 1 when reading. *2. transmit ack = 0 from the ma ster device to the rtc when reading. real - time data 2 access ? status register 1 access and status register 2 access *1. 0: status register 1 selected, 1: status register 2 selected *2. set no_ack = 1 when reading. status register 1 access and status regi ster 2 access ? int1 register access and int2 register access in reading / writing the int1 and int2 registers, data varies depending on the setting of the status register 2. be sure to r ead / write after setting the status register 2. when setting the alar m by using the status register 2, these registers work as 3 - byte alarm time data registers, in other statuses, they work as 1 - byte registers. when outputting the user - set frequency, they are the data registers to set up the frequency. regarding details of each data refer to " int1 register and int2 register " in " configuration of registers ".
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||| ||||||||| 2 015 - 12 - 000 1 pt0 280 - 8 12 / 11 /1 5 31 p t7c43390 /43390c real - time clock module caution: users cannot use both functions of alarm 1 interrupt and output of user - set frequency for the int1 pin and int2 pin simultaneously. *1. 0: int1 register select ed, 1: int2 register selected *2. set no_ack = 1 when reading. *3. transmit ack = 0 from the master device to the rtc when reading. int1 register access and int2 register access *1. 0: int1 register selected, 1: int2 register selected *2. set no_ack = 1 when reading. int1 register and int2 register (data register for output frequency) access ? clock correction register access *1. set no_ack = 1 when reading. clock correction register access
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||| ||||||||| 2 015 - 12 - 000 1 pt0 280 - 8 12 / 11 /1 5 32 p t7c43390 /43390c real - time clock module ? free register access *1. set no_ack = 1 when reading. free register access 12. reset after communication interruption in case of communication interruption in the pt7c43390, for example, during communication the power supply voltage drops so that only the master device is reset; the pt7c43390 does not operate the ne xt procedure because the internal circuit keeps the state prior to communication interruption. the pt7c43390 does not have a reset pin so that users usually reset its internal circuit by inputting a stop condition. i f the sda is outputting "l" (during outp ut of acknowledgment signal or reading) , t he pt7c 43390 does not accept a stop condition from the master device. in this case, users are necessary to finish acknowledgment output or reading of the sda. below figure shows how to reset. first, input a start c ondition from the master device (the pt7c43390 cannot detect a start condition because the sda in the pt7c43390 is outputting "l"). next, input a clock pulse equivalent to 7 - byte data access (63 - clock) from the scl. during this, release the sda line for th e master device. by this procedure, sda i/o before communication interruption is finished, so that the sda line in the pt7c43390 is released. after that, inputting a sto p condition resets the internal circuit so that restore the regular communication. this reset procedure is recommended to perform at initialization of the system after rising the master devices power supply voltage. figure how to reset
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||| ||||||||| 2 015 - 12 - 000 1 pt0 280 - 8 12 / 11 /1 5 33 p t7c43390 /43390c real - time clock module 13. flowchart of initialization and example of real - time data set - up *1. do not communicate for 0.5 s econds since the power - on detection circuit is in operation. *2. reading the real - time data 1 should be completed within 1 second after setting the real - time data 1. example of initialization flowchart
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||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||| ||||||||| 2 015 - 12 - 000 1 pt0 280 - 8 12 / 11 /1 5 38 p t7c43390 /43390c real - time clock module t dfn 4 .0x 4 .0 - 8 l ordering information part no. package code package pt7c433 90le l lead free and green 8 - pin tssop pt7c43390le x l lead free and green 8 - pin tssop tape/reel pt7c43390we w lead free and green 8 - pin soic pt7c43390we x w lead free and green 8 - pin soic tape/reel pt7c43390zee ze lead free and green 8 - pin tdfn 2x 3 PT7C43390CZEE ze lead free and green 8 - pin tdfn 4 x 4 note: ? e = pb - free and green ? adding x suffix = tape /r eel pericom semiconductor corporation ? 1 - 800 - 435 - 2336 ? www.pericom.com pericom reserves the right to make changes to its products or specifications at an y time, without notice, in order to improve design or performance and to supply the best possible product. pericom does not assume any responsibility for use of any circuitry described other than the circu itry embodied in pericom product. the company makes no representations that circuitry described herein is free from pate nt infringement or other rights of pericom .

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